Area-efficient distributed device structure for integrated voltage regulators
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsJoshipura Jwalant, Nitin Bansal, Amit Katyal, Massimiliano Picca
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Abstract
An area efficient distributed device for integrated voltage regulators comprising at least one filler cell connected between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is connected as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.
Claims30
An area efficient distributed device structure for integrated voltage regulators comprising:
- at least one filler cell connected between a pair of PADS on an I/O rail of a chip,
- at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip.
A method for creating a distributed device structure for integrated voltage regulators comprising steps of:
- coupling at least one filler cell between a pair of PADS on I/O rail of a chip,
- incorporating replicas of said device in additional filler cells, and
- connecting said additional filler cell to said I/O rails.
An integrated circuit, comprising:
- a periphery;
- first and second pads disposed within the periphery;
- a first filler cell disposed within the periphery between the first and second pads;
- and
- a voltage regulator having a component disposed within the first filler cell.
An integrated circuit, comprising:
- a periphery;
- first and second input-output blocks disposed within the periphery and having substantially a same size;
- a first pad disposed within the periphery and over one of the first and second input-output blocks;
- and
- a voltage regulator having a component disposed within the one of the first and second input-output blocks.
An electronic system, comprising:
- an integrated circuit, including
- a periphery,
- first and second pads disposed within the periphery, a first filler cell disposed within the periphery between the first and second pads, and
- a voltage regulator having a component disposed within the first filler cell.
An electronic system, comprising:
- an integrated circuit including
- a periphery,
- first and second input-output blocks disposed within the periphery and having substantially a same size,
- a first pad disposed within the periphery and over one of the first and second input-output blocks, and
- a voltage regulator having a component disposed within the one of the first and second input-output blocks.
A method, comprising:
- coupling a first node of an integrated circuit to a second node of the integrated circuit with a pass transistor disposed in a first filler cell that is located within a periphery of the integrated circuit between first and second pads of the integrated circuit;
- and
- controlling an impedance of the pass transistor to generate a regulated voltage on the second node from an input supply voltage on the first node.
A method, comprising:
- coupling a first node of an integrated circuit to a second node of the integrated circuit with a pass transistor disposed in a first input-output block that is located within a periphery of the integrated circuit that also includes a first pad disposed over the first input-output block and includes a second input-output block disposed within the periphery and having substantially the same size as the first input-output block;
- and
- controlling an impedance of the pass transistor to generate a regulated voltage on the second node from an input supply voltage on the first node.
Dependencies are inferred from the claim text.