Logic cell layout architecture with shared boundary
AssigneeIcera Inc.
InventorShannon Morton
Life of this patent
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Abstract
Logic cell layout architecture having a shared boundary between at least two cells each forming logic functions, and a method (200) for designing a logic cell library having a shared boundary between at least two cells (12,32) is disclosed for increasing packing density and limiting the occurrence of stress between active areas and shallow trench isolation (STI) regions of logic cells within a standard cell library for semiconductor integrated circuits (IC).
Claims42
A method for building an integrated circuit having a shared boundary cell architecture, comprising:
- providing a logic cell library having at least one cell each cell having a logic function defined by the interconnection between active regions, non-active regions and power rails of each logic cell and the non-active regions defining two edges of the cell;
- identifying a cell having an identified connection between an active region and the same respective power rail along an edge of each cell;
- and
- placing the identified cell in the integrated circuit and arranging the cell with an edge of the identified cell straddling the identified connection to form a boundary connection to share with another cell in the integrated circuit to form the shared boundary cell architecture.
A method for designing a logic cell library having cells with a shared boundary cell architecture, comprising:
- providing a first logic cell library having at least one cell, each cell having a logic function defined by the interconnection between active regions, non-active regions and power rails of each logic cell and the non-active regions defining two edges of the cell;
- identifying a cell having an identified connection between an active region and a power rail along an edge of each cell;
- and
- placing the identified cell in a second logic cell library and arranging the cell with an edge of the identified cell straddling the identified connection to form a boundary to share with another cell a connection from the active region to the same respective power rail, wherein the second logic cell library forms the logic cell library having cells with a shared boundary cell architecture.
A cell in an integrated circuit having a shared boundary with at least one other adjacent cell, the cell comprising a logic function defined by the interconnection between active regions, non-active regions and power rails of each logic cell;
- a connection between an active region and a respective power rail shared with the adjacent cell to form the shared boundary cell architecture.
A cell library having a shared boundary logic cell architecture, comprising a cell comprising a shared boundary capable of being shared with another adjacent cell, the cell comprising a logic function defined by the interconnection between active regions, non-active regions and power rails of each logic cell, an edge of the cell straddling a connection between an active region and a respective power rail forming a boundary connection capable of being shared with an adjacent cell in an integrated circuit to form the shared boundary cell architecture.
Dependencies are inferred from the claim text.