System and method for automatic insertion of on-chip decoupling capacitors

A computer program product in a computer readable medium for decoupling capacitor insertion in a circuit design, comprising:

• first instructions for obtaining circuit data identifying characteristics of the circuit design;
• second instructions for partitioning the circuit design into one or more cells based on the circuit data;
• third instructions for determining a voltage noise map for each cell of the one or more cells;
• fourth instructions for applying a required capacitance mapping function to the voltage noise map for each cell of the one or more cells to identify a required capacitance for each cell of the one or more cells;
• and
• fifth instructions for inserting one or more decoupling capacitors into at least one cell of the one or more cells based on the required capacitance for the at least one cell.

A system for decoupling capacitor insertion in a circuit design, comprising:

• one or more circuit design data sources;
• a circuit simulation engine coupled to the one or more circuit design data sources;
• and
• a decoupling capacitor insertion engine coupled to the circuit simulation engine, wherein the one or more circuit design data sources provide circuit data identifying characteristics of the circuit design, wherein the circuit simulation engine partitions the circuit design into one or more cells based on the circuit data and determines a voltage noise map for each cell of the one or more cells, and wherein the decoupling capacitor insertion engine applies a required capacitance mapping function to the voltage noise map for each cell of the one or more cells to identify a required capacitance for each cell of the one or more cells and inserts one or more decoupling capacitors into at least one cell of the one or more cells based on the required capacitance for the at least one cell.