Optimizing IC clock structures by minimizing clock uncertainty
AssigneeLSI Logic Corporation
InventorsAiguo Lu, Ivan Pavisic, Nikola Radovanovic
Life of this patent
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Abstract
A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.
Claims5
A process of optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins, comprising steps of:
- forcing a first buffer to a center of gravity of the plurality of leaves;
- inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations;
- and
- moving the first buffer to a center of gravity of the set of second buffers.
Dependencies are inferred from the claim text.