Apparatus and method for analyzing post-layout timing critical paths

A signal-propagating-path rendering apparatus, comprising:

• a critical-path detecting means for detecting a critical path on a basis of data concerning a design in which cells are placed on a chip of a semiconductor integrated circuit and information concerning a timing constraint on the chip;
• and
• a representative-critical-path extracting means for extracting a representative critical path by having one critical path represent critical paths which share more intervals than a certain number, and which are similar to one another, out of critical paths which have been detected by the critical path detecting unit, and for displaying the representative critical path.

A signal-propagating-path rendering method which causes a computer to render a signal-propagating-path of a semiconductor integrated circuit, the method comprising:

• a first step of causing the computer to detect critical paths on a basis of data concerning a design in which cells are placed on a chip of a semiconductor integrated circuit and information concerning a timing constraint on the chip, and to store the critical paths in a memory;
• a second step of causing the computer to read out the critical paths from the memory, thus extracting a representative critical paths in a memory by having one critical path represent critical paths which share more intervals than a certain number, and which are similar to one another, out of the critical paths which have been read out from the memory, thus storing the representative critical path in the memory and
• a third step of causing the computer to read out the representative critical paths from the memory, and to render the representative critical path while reflecting, on the representative critical paths, information concerning other critical paths which are similar to the representative critical path.