Frequency dependent timing margin

A method for determining a timing margin to be applied in an integrated circuit timing design, the method comprising the steps of:

• determine circuit simulator path delays for the integrated circuit timing design,
• determine static timing analysis tool path delays for the integrated circuit timing design,
• plot in a first plot the circuit simulator path delays versus a percentage difference between the circuit simulator path delays and the static timing analysis tool path delays,
• plot in a second plot the circuit simulator path delays versus a numerical difference between the circuit simulator path delays and the static timing analysis tool path delays,
• identify a first point on the second plot having a largest numerical difference,
• identify the circuit simulator path delay for the first point,
• find a corresponding point on the first plot having the circuit simulator path delay,
• identify the percentage difference for the corresponding point, and
• use a combination of both the circuit simulator path delay and the percentage difference as the timing margin,
• wherein the circuit simulator path delay is held constant and the percentage difference is varied to achieve the timing margin.

A method for determining a timing margin to be applied in an integrated circuit timing design, the method comprising the steps of:

• determine circuit simulator path delays for the integrated circuit timing design,
• determine static timing analysis tool path delays for the integrated circuit timing design,
• plot in a first plot the circuit simulator path delays versus a percentage difference between the circuit simulator path delays and the static timing analysis tool path delays,
• plot in a second plot the circuit simulator path delays versus a numerical difference between the circuit simulator path delays and the static timing analysis tool path delays,
• identify a first point on the second plot having a largest numerical difference,
• identify the circuit simulator path delay for the first point,
• find a corresponding point on the first plot having the circuit simulator path delay,
• identify the percentage difference for the corresponding point, and
• use a combination of both the circuit simulator path delay and the percentage difference as the timing margin,
• wherein the circuit simulator path delay is varied and the percentage difference is held constant to achieve the timing margin.