Semiconductor device design system and method, and software product for the same
AssigneeNEC Electronics Corporation
InventorKenta Yamada
Life of this patent
Estimating the term…
Abstract
A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured to store parameters indicating the parasitic resistance and the parasitic capacitance in relation to the target interconnection to each of the plurality of patterns. The producing is achieved by calculating the parameters to a plurality of conditions corresponding to deviation in manufacture of the wiring structure for each of the plurality of patterns.
Claims20
A computer-readable software product comprising codes, executed by a computer, for a method of determining parasitic resistance and capacitance from a layout of an LSI, said method comprising:
- providing a plurality of patterns of a wiring structure which contains a target interconnection;
- and
- producing a library configured to store parameters indicating said parasitic resistance and said parasitic capacitance in relation to said target interconnection to each of said plurality of patterns,
- wherein said producing comprises:
- calculating said parameters to a plurality of conditions corresponding to deviation in manufacture of said wiring structure for each of said plurality of patterns.
A computer-readable software product comprising codes, executed by a computer, for a method of determining parasitic resistance and capacitance from a layout of an LSI, by referring a library, wherein a wiring structure which contains a target interconnection is a pattern, and said library stores parameters indicating said parasitic resistance and said parasitic capacitance in relation to said target interconnection to a plurality of conditions for variation in manufacture of said wiring structure with respect to each of a plurality of said patterns, said method comprising:
- reading a netlist of said LSI;
- reading a layout data indicating said layout of said LSI;
- calculating said parasitic resistance and said parasitic capacitance in each of said plurality of conditions to each of said interconnections contained in said layout by referring to said parameters stored in said library;
- and
- generating a netlist with parasitic RC by adding the calculated parasitic resistance and the calculated parasitic capacitance to said netlist.
A method of manufacturing a semiconductor device which has a plurality of wiring layers, comprising:
- determining design criteria, and a manufacturing condition of said semiconductor device;
- carrying out layout design of said semiconductor device based on functional specification and said design criteria to produce a layout data;
- estimating process variations of width and thickness of each of interconnections for every wiring layer from said layout data based on said design criteria and said manufacturing condition;
- determining an interconnection delay affected by a specific condition of said process variations for every wiring layer;
- repeating correction of said layout data, the estimation and the determination until the determined interconnection delay meets said function specification, to produce a final layout data;
- and
- manufacturing said semiconductor device based on said final layout data and said manufacture condition,
- wherein said determining an interconnection delay comprises:
- determining a variation of said interconnection delay by using of parasitic resistance and parasitic capacitance for every wiring layer through statistical relaxation in which the process variations of width and thickness of each of interconnections are independent between said plurality of wiring layers.
Dependencies are inferred from the claim text.