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AssigneeInternational Business Machines Corporation
InventorsRobert Likovich, Joseph Mendenhall, John Morris, David Otero, Chad Winemiller
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Methods, systems, and media for managing functional verification of a parameterizable design are disclosed. Embodiments include a system having a testbench configuration module adapted to configure a testbench, the testbench having testbench signals and one or more instantiated components having a plurality of ports of a generic design, where the testbench signals are wired to the plurality of ports. The testbench may also have one or more instantiated special components based on chip-specific versions of the design where the special components are wired to the same ports as the generic design. The system may also include a functional verification manager that, through a component module, observes values in the testbench and automatically configure a verification environment based on the observed values, including automatic insertion of checkers at different levels of hierarchy. The testbench may be a VHDL or Verilog testbench in some embodiments.
A method for managing functional verification of a parameterizable design, the method comprising:
A machine-accessible medium containing instructions effective, when executing in a data processing system, to cause said data processing system to perform operations comprising:
A system for managing functional verification of a design, the system comprising:
Dependencies are inferred from the claim text.