Resistance extraction for hierarchical circuit artwork

A number of machine-readable media having stored thereon sequences of instructions that, when executed by a machine, cause the machine to extract resistance from hierarchical circuit artwork comprised of parent and child circuit blocks by performing actions comprising:

• for each child circuit block,
• identifying at least one portion of signal trace artwork to which a parent circuit block may connect;
• marking the identified portions of signal trace artwork as deferred artwork;
• extracting resistance for the child circuit block less the deferred artwork;
• and
• for each identified portion of signal trace artwork, defining a port where deferred artwork adjoins artwork for which resistance has been extracted;
• and
• for each parent circuit block,
• promoting deferred artwork from child circuit blocks to which the parent circuit block connects;
• and
• extracting resistance for the parent circuit block, including the promoted artwork.

An integrated circuit produced by:

• generating hierarchical circuit artwork comprised of parent and child circuit blocks;
• for each child circuit block,
• identifying at least one portion of signal trace artwork to which a parent circuit block may connect;
• marking the identified portions of signal trace artwork as deferred artwork;
• extracting resistance for the child circuit block less the deferred artwork;
• and
• for each identified portion of signal trace artwork, defining a port where deferred artwork adjoins artwork for which resistance has been extracted;
• for each parent circuit block,
• promoting deferred artwork from child circuit blocks to which the parent circuit block connects;
• and
• extracting resistance for the parent circuit block, including the promoted artwork;
• and
• optimizing the hierarchical circuit artwork in response to analysis of the extracted resistances.