Event driven switch level simulation method and simulator
AssigneeSamsung Electronics Co., Ltd.
InventorsSeuk-Whan Lee, Moon-Hyun Yoo, Joon-Ho Choi
Life of this patent
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Abstract
A method for simulating an integrated circuit includes performing a power supply voltage tuning operation to find a power supply voltage at which a simulation of the integrated circuit at an operating frequency passes a functional requirement, identifying a weak signal node based on the simulation result, and performing a size tuning operation on the weak signal node of the integrated circuit.
Claims20
A method for simulating an integrated circuit, comprising:
- performing a power supply voltage tuning operation to find a power supply voltage at which a simulation of the integrated circuit at an operating frequency passes a functional requirement;
- identifying a weak signal node based on the simulation result;
- and
- performing a size tuning operation on the weak signal node of the integrated circuit.
A simulation method to find a power supply voltage for an integrated circuit, comprising:
- setting a maximum power supply voltage and a minimum power supply voltage;
- setting an operating voltage to a voltage corresponding to half the sum of the maximum power supply voltage and the minimum power supply voltage;
- generating a technology file for analyzing parameters of the integrated circuit;
- simulating using the technology file, a netlist of the integrated circuit, the operating voltage, and a simulation vector;
- setting the minimum power supply voltage to the operating voltage if the simulation result fails;
- and
- setting the maximum power supply voltage to the operating voltage if the simulation result passes.
A simulation method for detecting a weak node of an integrated circuit, comprising:
- simulating the integrated circuit;
- counting transitions of signal nodes of the integrated circuit;
- forming a function sensitivity list based on the counted number of transitions;
- and
- detecting the weak node in response to the function sensitivity list.
A simulation method for detecting a weak signal node of an integrated circuit comprising:
- calculating delay time variations and load variations of signal nodes of the integrated circuit with respect to a variation in an operating voltage;
- dividing the delay time variations by the load variations to obtain resistance variations;
- forming a timing sensitivity list based on the resistance variations of the signal nodes;
- and
- detecting the weak node in response to the timing sensitivity list.
An apparatus for simulating an integrated circuit, comprising:
- a power supply voltage tuning unit configured to perform a power supply voltage tuning operation to find a power supply voltage at which a simulation of the integrated circuit at an operating frequency passes a functional requirement;
- a weak node identifying unit configured to identifying a weak signal node based on the simulation result;
- and
- a size tuning unit configured to perform size tuning on the weak signal node of the integrated circuit.
Dependencies are inferred from the claim text.