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US 2006/0190851 A1Published application
Asynchronous circuit design tool and computer program product
AssigneeSeiko Epson Corporation
InventorsNobuo Karaki, Tak Lee
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AssigneeSeiko Epson Corporation
InventorsNobuo Karaki, Tak Lee
Estimating the term…
It is the object of the present invention to provide asynchronous circuit design tools for those engineers who are versed in standard hardware description languages (HDLs), which is widely used in industry mainly for synchronous circuit design, to design asynchronous circuits with relative ease. To accomplish the object, the asynchronous circuit design tools of the present invention include a translator for transforming a code written in an asynchronous circuit design language, which is based on a standard HDL and includes minimal primitives for describing the communications between asynchronous circuit blocks or processes, into a code written in a standard HDL, which is originally developed for synchronous circuit design. The codes transformed into the standard HDL can be functionally verified by using commercially available simulators, which are originally developed for verifying synchronous circuit design.
An asynchronous circuit design tool comprising a translator for transforming a code written in an asynchronous circuit design language, which is based on the subset of a standard hardware description language (HDL) and includes minimal primitives used for describing the communications between asynchronous circuit blocks or processes, into a code written in a standard HDL that is originally developed for synchronous circuit design.
An asynchronous circuit design tool comprising a dedicated simulator for performing functional verification of an asynchronous circuit designs written in the asynchronous circuit design language, which is based on the subset of the standard HDL and includes the minimal primitives used for describing the communications between asynchronous circuit blocks or processes.
An asynchronous circuit design tool comprising a logic synthesis tool that translates a code written in an asynchronous circuit design language, which is based on the subset of a standard HDL and includes minimal primitives used for describing the communications between asynchronous circuit blocks or processes, into a gate level implementation or netlist, which gives information for connecting elements;
A computer program product comprising a computer program, that enables a computer system to function as transformation means to transform a code written in the asynchronous circuit design language, which includes primitives used for describing the communications between asynchronous circuit blocks or processes, into a code written in a HDL that is originally developed for synchronous circuit design.
A computer program product comprising a computer program that enables a computer system to function as simulation means to perform functional verification of synchronous circuit designs written in the asynchronous circuit design language, which is based on a standard HDL and includes minimal primitives used for describing the communications between asynchronous circuit blocks or processes.
A computer program product comprising a computer program that enables a computer system to function as simulation means to pre-compile or transform a code written in the asynchronous design language, which is based on the subset of a standard HDL and includes minimal primitives for communications between asynchronous circuit blocks or processes, into a code written in an intermediate language that is directly executed inside the software.
A computer program product comprising a computer program that enables a computer system to function as simulation means to interpret and execute the source code statement by statement, even without pre-compilation means, for functional verification of asynchronous circuit designs written in the asynchronous circuit design language, which is based on the subset of a standard HDL and includes minimal primitives for communications between asynchronous circuit blocks or processes.
A computer program product comprising a computer program that enables a computer system to function as logic synthesis means for transforming a code written in the asynchronous circuit design language, which is based on the subset of a standard HDL and includes minimal primitives used for describing the communications between asynchronous circuit blocks or processes, into a gate level implementation or netlist, which gives information for connecting elements;
Dependencies are inferred from the claim text.