Low power consumption designing method of semiconductor integrated circuit

A low power consumption designing method of a semiconductor integrated circuit, comprising:

• a standard cell synthesizing step of synthesizing a net list from an RTL (register transfer level) description of a circuit structure so as to form an instance name list which contrasts a register description portion contained in the RTL description with an instance name;
• a simulation step of inputting thereinto an applied actual operation pattern so as to perform an operation simulation written by the RTL description;
• a toggle storing step of recording toggle information among registers extracted in the simulation step;
• a mapping step of constituting flip-flop-to-flip-flop toggle information database in which the toggle information acquired from the toggle storing step corresponds to a flip-flop-to-flip-flop instance name acquired from the instance name list;
• and
• an electric power optimizing step of optimizing a physical designing operation in order to reduce power consumption by employing the net list, the flip-flop-to-flip-flop toggle information database, and an arbitrarily applied timing restriction.