IC compaction system

A method for compacting a layout for an integrated circuit (IC) comprising a plurality of cell instances, each cell instance describing a structure of a separate electronic device to be incorporated into the IC, and a plurality of path objects, each path object describing a structure for interconnecting electronic devices to be incorporated into the IC,

• wherein an internal layout of each cell instance includes a plurality of device objects each corresponding to a separate portion of IC material to form the corresponding electronic device, a shape and position of each device object within the internal layout of the cell instance defining a shape and position of its corresponding portion of IC material within the electronic device described by the cell instance,
• wherein device objects and path objects is bounded by a plurality of edges, and
• wherein distances between edges of path and device objects are subject to constraints imposed by a set of design rules,
• the method comprising the steps of:
• a. creating a set of device rules indicating how modifications to internal layouts of the cell instances can be made without affecting a behavior of the electronic devices the cell instances describe, and
• b. compacting the IC layout in accordance with the design rules and the device rules by repositioning cell instances and path objects within the layout, by modifying path objects, and by modifying the internal layout of at least one cell instance of the plurality of cell instances.