Synchronization point across different memory BIST controllers

A method of testing multiple memories, comprising:

• providing a first BIST controller within an integrated circuit, the first BIST controller coupled with a first group of memories, wherein the first BIST controller comprises an additional second BIST controller that is coupled with a second group of memories;
• using the first BIST controller, performing a first phase of a memory test on the first group of memories;
• upon completion of the first phase of the memory test in the first BIST controller, entering an idle state, wherein the first BIST controller enters the idle state under its own initiative;
• using the second BIST controller, performing a first phase of a memory test on the second group of memories, independent of the first BIST controller;
• upon completion of the first phase of the memory test in the second BIST controller, entering an idle state, wherein the second BIST controller enters the idle state under its own initiative;
• coupling a first resume input on the integrated circuit with the first BIST controller and a second resume input on the integrated circuit with the second BIST controller, wherein the first resume input and the second resume input each comprise an input pin to the integrated circuit, and wherein a first resume signal on the first resume input and a second resume signal on the second resume input are each asserted through channels between automated test equipment (ATE) and the integrated circuit;
• and
• in response to activation of the first and second resume inputs, exiting the idle state in the first and second BIST controllers.