Method and apparatus for verifying memory testing software

A computer program product residing on a computer usable medium for verifying the accuracy of logical-to-physical mapping software designed for testing memory devices, said computer program product comprising:

• program code means for utilizing a built-in self test (BIST) fail control function to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device;
• program code means for testing said memory array via a memory tester;
• program code means for generating a bit fail map by said logical-to-physical mapping software based on all memory fails indicated by said memory tester, wherein said bit fail map indicates physical locations of all fail memory locations derived by said logical-to-physical mapping software;
• and
• program code means for comparing said fail memory locations derived by said logical-to-physical mapping software to said various predetermined memory locations to verify the accuracy of said logical-to-physical mapping software.

A built-in self-test (BIST) unit for verifying a logical-to-physical transform algorithm designed to test integrated circuit memory devices, said BIST unit comprising:

• a built-in self test (BIST) fail control module for generating a plurality of simulated memory fails at various predetermined locations within a memory array of a memory device;
• means for testing said memory array via a memory tester;
• means for generating a bit fail map by said logical-to-physical mapping software based on all memory fails indicated by said memory tester, wherein said bit fail map indicates physical locations of all fail memory locations derived by said logical-to-physical mapping software;
• and
• means for comparing said fail memory locations derived by said logical-to-physical mapping software to said various predetermined memory locations to verify the accuracy of said logical-to-physical mapping software.