US 2006/0190786 A1 · Semiconductor integrated circuit and method of tesiting semiconductor integrated circuit

Abstract

A semiconductor integrated circuit having an internal circuit which is tested based on a scanning method is provided. The internal circuit has: memory elements including a first memory element and a second memory element; combinational circuits including a first combinational circuit receiving an external input data, a second combinational circuit outputting an external output data and a third combinational circuit; a first selection circuit; and a second selection circuit. The first selection circuit receives the external input data and a stored data held by the first memory element, and outputs any of them to the first combinational circuit. The second selection circuit receives the external output data output from the second combinational circuit and an operation result data output from the third combinational circuit, and outputs any of them to the second memory element.

Claims14

Dependent claims

A semiconductor integrated circuit having an internal circuit which is tested based on a scanning method,

said internal circuit comprising:
a plurality of memory elements including a first memory element and a second memory element;
a plurality of combinational circuits including a first combinational circuit to which an external input data is input, a second combinational circuit outputting an external output data and a third combinational circuit;
a first selection circuit configured to receive said external input data and a stored data held by said first memory element, and to output any of said external input data and said stored data to said first combinational circuit;
and
a second selection circuit configured to receive said external output data output from said second combinational circuit and an operation result data output from said third combinational circuit, and to output any of said external output data and said operation result data to said second memory element.

3 more elements

A method of testing an internal circuit of a semiconductor integrated circuit based on a scanning method,

said internal circuit having:
a plurality of memory elements including a first memory element and a second memory element;
and
a plurality of combinational circuits including a first combinational circuit to which an external input data is input, a second combinational circuit outputting an external output data and a third combinational circuit, wherein an output of said second memory element is connected to an input of one of said plurality of combinational circuits,
said method comprising:
(A) testing said internal circuit in a first test mode;
and
(B) testing said internal circuit in a second test mode,
wherein in said (A) testing, a stored data held by said first memory element is input to said first combinational circuit instead of said external input data, and an operation result data output from said third combinational circuit is held by said second memory element, and
wherein in said (B) testing, a stored data held by said first memory element is input to said first combinational circuit instead of said external input data, and said external output data output from said second combinational circuit is held by said second memory element.

7 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuit and method of tesiting semiconductor integrated circuit

Life of this patent

Semiconductor integrated circuit and method of tesiting semiconductor integrated circuit

Life of this patent

Abstract

Claims14