Method and circuit using boundary scan cells for design library analysis
AssigneeInternational Business Machines Corporation
InventorsPamela Gillis, David Litten, Steven Oakland
Life of this patent
Estimating the term…
Abstract
A boundary scan register circuit and a method of characterization testing. The boundary scan register circuit, including: a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch; means for isolating the boundary scan cells into one or more boundary scan segments, each boundary scan segment containing a different set of the boundary scan cells; and means for characterizing signal propagation through each the boundary scan segment.
Claims20
A boundary scan register circuit, comprising:
- a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch;
- means for isolating said boundary scan cells into one or more boundary scan segments, each boundary scan segment containing a different set of said boundary scan cells;
- and
- means for characterizing signal propagation through each said boundary scan segment.
A method of characterizing elements of a boundary scan cell, comprising:
- providing a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch;
- isolating said boundary scan cells into one or more boundary scan segments, each boundary scan segment containing a different set of said boundary scan cells;
- and
- characterizing signal propagation through each said boundary scan segment.
A method of characterizing elements of a boundary scan cell of a boundary scan register used for testing interconnections of an integrated circuit chip, comprising:
- providing a set of boundary scan cells connected in series to form a boundary scan register, a test data output pin of each previous boundary scan cell of said boundary scan register coupled to a test data input pin of an immediately subsequent boundary scan cell of said boundary scan register, each boundary scan cell coupled between a different integrated circuit chip input/output pad and a corresponding core logic circuit pin of said core logic circuit, each boundary scan cell having a latch, each said latch having a latch mode and a flush mode;
- isolating said boundary scan cells into one or more boundary scan segments, each boundary scan segment containing a different sub-set of said set of boundary scan cells;
- and
- characterizing signal propagation through each said boundary scan segment.
Dependencies are inferred from the claim text.