Clock control circuit for test that facilitates an at speed structural test
AssigneeInternational Business Machines Corporation
InventorsHenry Farmer, Gary Grise, David Milton, Mark Taylor
Life of this patent
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Abstract
When testing an ASIC using functional clocks, a control circuit at the clock root incorporates additional test logic in the root and a deskewer for clock control, giving rise to a very flexible control that can pass clock signals at a number of clock rates and can pass only a single clock edge, thereby permitting the passage of the required number of clock pulses for a test. The system uses the functional clock and the clock distribution tree designed into the ASIC.
Claims37
A method of performing a structural at speed test of discrete logic elements within an integrated circuit, wherein the logic elements are synchronized with a plurality of clock domains, the method comprising:
- coupling a clock control circuit for test to a primary clock generator (PLL) for clock control;
- providing control circuitry within the clock control circuit for test to generate multiple test clock signals for a plurality of downstream functional logic paths within the integrated circuit;
- providing test logic within the clock control circuit for test circuit for the plurality of functional logic paths;
- selecting a clock configuration for a selected one of the plurality of functional logic paths;
- performing an at speed test of a functional logic path via the selected clock configuration;
- and continuing the operation of the primary clock generator during the at speed test.
A method of performing a structural at speed test of discrete logic elements within an integrated circuit, wherein the logic elements are synchronized with a plurality of clock domains, the method comprising:
- replacing a downstream clock divider controlling the clock input to at least one of said plurality of clock domains with a clock control circuit for test.
Apparatus for performing a structural at speed test of discrete logic elements within an integrated circuit, wherein the logic elements are synchronized with a plurality of clock domains, comprising:
- a clock control circuit for test coupled to a primary clock generator (PLL) for clock control;
- control circuitry within the clock control circuit for test to generate multiple test clock signals for a plurality of downstream functional logic paths within the integrated circuit;
- test logic within the clock control circuit for test circuit for the plurality of functional logic paths;
- selection circuitry for selecting a clock configuration for a selected one of the plurality of functional logic paths and applying said selected clock configuration to at speed test of a functional logic path while the operation of the primary clock generator continues in operation during the at speed test.
Dependencies are inferred from the claim text.