Method for reducing SRAM test time by applying power-up state knowledge

Abstract

Methods (400, 500, and 600) are disclosed for testing a memory device by tailoring an algorithm (460) used in the testing based on the preferred or intrinsic data state 425 that is obtained upon power-up of an advanced technology SRAM memory device (100). The methods (400, 500, and 600) take advantage of the observation that such SRAM devices repeatedly power-up in a preferred state 310. Accordingly, one method 500 comprises powering-up 510 the memory device and reading 520 a preferred power-up data state of each cell of the memory device without memory initialization or writes. The method 500 then captures and stores 530 a data state associated with the preferred power-up data state of each cell 100 and utilizes the stored power-up data state 310 or an inverse of the power-up data state 320 to tailor 540 a test pattern used by the test algorithm 460. For example, specific 0 and 1 test pattern data in the algorithm may be replaced by the power-up data state 310 or an inverse of the power-up data state 320. In this way, further reading of the memory cell 100 in the preferred data state is unnecessary allowing reduced testing times, particularly in the case of data retention and cell disturb testing times.

Dependencies are inferred from the claim text.