Method and system for correcting errors in read-only memory devices, and computer program product therefor
AssigneeSTMicroelectronics S.r.l.
InventorsNicolas Grossier, Chilakala Kumar, Saverio Pezzini
Life of this patent
Estimating the term…
Abstract
A system for correcting errors in read-only memory devices by means of memory patches, wherein patch data is used as read data in the place of erroneous data stored at a given location in the memory. The system includes a processing core, such as an ARM processor, adapted to perform opcode accesses as well as data accesses to memory addresses being patched. The processing core is configured for providing different patch-data for correcting errors depending on whether it is performing a code access or a data access to an address being patched.
Claims20
A method of correcting errors in a memory device using memory patches, wherein patch data is used as read data in the place of erroneous data stored at a given location in said memory, the method comprising the steps of:
- providing a processing core structured to perform opcode accesses as well as data accesses to memory addresses being patched;
- and
- providing different patch-data for correcting errors depending on whether said core is performing a code access or a data access to an address being patched.
A computer system, comprising:
- a memory device having a storage location that stores erroneous data;
- and
- a processing core structured to perform opcode accesses as well as data accesses to memory addresses being patched, said processing core being configured for providing different patch-data for correcting errors depending on whether said core is performing a code access or a data access to an address of the memory device being patched.
A computer-readable medium including code portions that cause a computing device to correct errors in a memory device using memory patches, wherein patch data is used as read data in the place of erroneous data stored at a given location in said memory, by performing a method comprising:
- performing, using a processing core, opcode accesses as well as data accesses to memory addresses being patched;
- and
- providing different patch-data for correcting errors depending on whether said core is performing a code access or a data access to an address being patched.
A computer system, comprising:
- a memory device having a storage location that stores erroneous data;
- a patch data memory storing patch data;
- a patch code memory store a patch code instruction;
- a processor structured to perform opcode accesses as well as data accesses to memory addresses being patched;
- and
- selection means for selectively providing to the processor either the patch data from the patch data memory or the patch code instruction from the patch code memory depending on whether the processor is performing a code access or a data access to an address of the memory device being patched.
Dependencies are inferred from the claim text.