Signals crossing multiple clock domains

A method for monitoring multiple clock domains, comprising:

• receiving different sets of signals to a multiplexer associated with a first source clock domain on an application specific integrated circuit (ASIC);
• using the multiplexer to select a set of signals from among the different sets of signals;
• loading selected sets of signals into a clock crossing first in first out (FIFO) associated with the first source clock domain, the clock crossing FIFO using the source clock domain and unloaded using a destination clock domain, wherein the destination clock domain has a higher clock frequency than a clock associated with the first source clock domain;
• and
• pipelining the selected sets of signals from an output of the clock crossing FIFO to another location on the ASIC.

A method for monitoring multiple clock domains, comprising:

• receiving different sets of signals to a multiplexer associated with a first source clock domain on an application specific integrated circuit (ASIC) to select a set of signals from among the different sets of signals;
• loading selected sets of signals from the first source clock domain into a clock crossing first in first out (FIFO) associated with a first source clock domain, the clock crossing FIFO using the source clock domain and unloaded using a destination clock domain, wherein the destination clock domain has a higher clock frequency than a clock associated with the first source clock domain;
• receiving different sets of signals to a multiplexer associated with a second source clock domain on the ASIC to select a set of signals from among the different sets of signals;
• loading selected sets of signals from the second source clock domain into a clock crossing FIFO associated with the second source clock domain, the clock crossing FIFO using the source clock domain and unloaded using the destination clock domain, wherein the destination clock domain has a lower clock frequency than a clock associated with the second source clock domain;
• connecting an output of the clock crossing FIFO associated with the first source clock domain and an output of the clock crossing FIFO associated with the second source clock domain to a multiplexer;
• and
• connecting selected sets of signals from the destination clock domain to the multiplexer.

An application specific integrated circuit (ASIC), comprising:

• a number of different clock domains located on different portions of the ASIC;
• a number of input/output (I/O) ports to couple signals to and from the ASIC;
• and
• a subset of the number of different clock domains each including:
• a multiplexer to select a set of signals from among different sets of signals within each respective clock domain;
• and
• a clock crossing first in first out (FIFO) to receive selected sets of signals within each respective clock domain, the FIFO using a source clock domain to load and using a destination clock domain to unload in order to allow the selected sets of signals to be moved to the destination clock domain.

An application specific integrated circuit (ASIC), comprising:

• a number of different clock domains located on different portions of the ASIC;
• a number of input/output (I/O) ports to couple signals to and from the ASIC;
• and
• means for moving internal signals from a subset of the number of different clock domains of multiple frequencies to a different clock domain for monitoring, observation, counting, and debug.