Monitoring multiple clock domains
OwnerJohn Wickeraadinventor
Life of this patent
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Abstract
Methods, systems, and circuits are provided for monitoring multiple clock domains. One method for monitoring multiple clock domains includes pipelining different sets of signals from different clock domains on an application specific integrated circuit (ASIC) to a particular input/output (I/O) port on the ASIC using an associated clock from each different clock domain, and selecting a particular set of signals from among the different sets of signals to send out of the particular I/O port.
Claims26
A method for monitoring multiple clock domains, comprising:
- pipelining different sets of signals from different clock domains on an application specific integrated circuit (ASIC) to a particular input/output (I/O) port on the ASIC using an associated clock from each different clock domain;
- and
- selecting a particular set of signals from among the different sets of signals to send out of the particular I/O port.
A method for monitoring multiple clock domains on an application specific integrated circuit (ASIC), comprising:
- pipelining different sets of signals from different clock domains on the ASIC to a particular input/output (I/O) port on the ASIC using an associated clock from each different clock domain;
- and
- using a multiplexer to select a particular set of signals from among the different sets of signals to send out of the particular I/O port.
A method for monitoring multiple clock domains on an application specific integrated circuit (ASIC), comprising:
- pipelining different sets of signals from at least two different clock domains on the ASIC to a particular I/O port which is shared as a flash random access memory (RAM) port and as a monitoring port using an associated clock from each different clock domain;
- using a first multiplexer to select between using the particular I/O port as the flash RAM port and using the particular I/O port as the monitoring port;
- and
- using a second multiplexer to select a particular set of signals from among the different sets of signals to send out of the particular I/O port and to select the associated clock for the particular set of signals, when the particular I/O port is being used as the monitoring port.
An application specific integrated circuit (ASIC), comprising:
- a number of different clock domains located on different portions of the ASIC;
- a number of input/output (I/O) ports to connect signals to and from the ASIC;
- circuitry to pipeline different sets of signals from the different clock domains to a particular input/output (I/O) port on the ASIC along with an associated clock from each of the different clock domains;
- and
- a multiplexer connecting the circuitry to the particular I/O port, wherein the multiplexer can select a particular set of signals from among the different sets of signals to send out of the particular I/O port.
An application specific integrated circuit (ASIC), comprising:
- a number of different clock domains located on different portions of the ASIC;
- a number of input/output (I/O) ports to connect signals to and from the ASIC;
- circuitry to pipeline different sets of signals from at least two different clock domains on the ASIC, along with an associated clock from each of the different clock domains, to a particular I/O port which is shared as a flash random access memory (RAM) port;
- a first multiplexer to select between using the particular I/O port as the flash RAM port and using the particular I/O port as the monitoring port;
- and
- a second multiplexer connecting the circuitry to the particular I/O port, the second multiplexer to select a particular set of signals from among the different sets of signals to send out of the particular I/O port and to select the associated clock for the particular set of signals, when the particular I/O port is being used as the monitoring port.
An application specific integrated circuit (ASIC), comprising:
- a number of different clock domains located on different portions of the ASIC;
- a number of input/output (I/O) ports to connect signals to and from the ASIC;
- means for pipelining different sets of signals from the different clock domains to a particular input/output (I/O) port on the ASIC along with an associated clock from each of the different clock domains;
- and
- means for selecting a particular set of signals from among the different sets of signals to send out of the particular I/O port.
Dependencies are inferred from the claim text.