Clock recovery systems and methods for adjusting phase offset according to data frequency

Abstract

A clock recovery system includes a sampler that is configured to sample an input data signal in synchronization with a modulated clock signal to generate a sample of the input data signal. A phase comparator is configured to compute a position of a transition edge of the input data signal using the sample data signal, and to compare the computed position with a position of an edge of the modulated clock signal to generate a comparison result. An edge counter is configured to count transition edges of the sample data signal. A controller is configured to generate first and second control signals based on the comparison result and the count of the transition edges. A clock phase modulator is configured to generate the modulated clock signal by adjusting a phase of an input clock signal responsive to the first and second control signals, such that the phase is increased in response to the first control signal and reduced in response to the second control signal.

Dependencies are inferred from the claim text.