Multifunction hexadecimal instruction form
AssigneeInternational Business Machines Corporation
InventorsEric Schwarz, Ronald Smith
Life of this patent
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Abstract
A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.
Claims33
A computer system instruction, comprising a fused hexadecimal floating point instruction consisting of MULTIPLY AND ADD which enables execution as op1=op3.op2+op1.
A computer system instruction, comprising:
- a fused hexadecimal floating point instruction consisting of MULTIPLY AND ADD which enables execution as op1=op3.op2−op1.
A computer system storage medium having a plurality of instructions, including:
- an instruction consisting of MULTIPLY AND ADD operations and an instruction consisting of MULTIPLY AND SUBTRACT operations which enable execution of op1=op3.op2±op1.
A computer system unit, comprising:
- A floating-pint unit supporting dual hexadecimal floating point (HFP) and IEEE 754 binary floating point (BFP) architectures and six formats including single, double, and quadword formats and having a fused multiply-add dataflow wherein a third operand is multiplied by a second operand, and then a first operand is added to or subtracted from the product.
A computer system, comprising:
- a storage medium and computer architected instructions stored in a computer storage medium, for producing the execution of the computer architected instructions by a running of a processor utilizing computer software having architected instructions to be executed, and comprising the instruction code which is stored in a computer storage medium, and wherein the first part of the instruction code comprises an operation code which specified the operation to be performed and a second part which designates the operands for that participate, and were at least some of said instructions provide opcodes for performing hexadecimal floating point and binary floating point operations as MULTIPLY AND ADD operations and an instruction consisting of MULTIPLY AND SUBTRACT operations which enable execution of op1=op3.op2±op1;
- and
- a decoder for decoding said instructions and an execution unit for execution said computer architected instructions.
Dependencies are inferred from the claim text.