Processor utilizing novel architectural ordering scheme
AssigneeIntel Corporation
InventorsJeffery Baxter, Gary Hammond, Nazar Zaidi
Life of this patent
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Abstract
Various methods, apparatuses, and systems in which a processor includes an issue engine and an in-order execution pipeline. The issue engine categorizes operations as at least one of either a speculative operation which perform computations or an architectural operation which has potential to fault or cause an exception. Each architectural operation issues with an associated architectural micro-operation. A first micro-operation checks whether a first speculative operation is dependent upon an intervening first architectural operation. The in-order execution pipeline executes the speculative operation, the architectural operation, and the associated architectural micro-operations.
Claims11
An apparatus, comprising:
- an out of order issue engine that has a set of micro-operations that the out of order issue engine issues using two different sets of architectural semantics;
- a first set of architectural semantics that includes speculative operations that can be issued whenever their operand data is available;
- and
- a second set of architectural semantics that includes architectural operations that issue after all earlier architectural operations in program order have been issued and all previous speculative operations associated with this architectural operation have issued.
A computer system, comprising:
- a processor having an out of order issue engine that has a set of micro-operations that the out of order issue engine issues using two different sets of architectural semantics;
- a first set of architectural semantics that includes speculative operations that can be issued whenever their operand data is available;
- a second set of architectural semantics that includes architectural operations that issue after all earlier architectural operations in program order have been issued and all previous speculative operations associated with this architectural operation have issued;
- a data bus coupled to the processor;
- and
- a memory coupled to the data bus.
A method of operating a processor, comprising:
- issuing a set of micro-operations using out of order issue engine and two different sets of architectural semantics by:
- issuing speculative operations whenever their operand data is available;
- and
- issuing architectural operations after all earlier architectural operations in program order have been issued and all previous speculative operations associated with this architectural operation have issued.
Dependencies are inferred from the claim text.