Processor utilizing novel architectural ordering scheme
AssigneeIntel Corporation
InventorsJeffery Baxter, Gary Hammond, Nazar Zaidi
Life of this patent
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Abstract
Various methods, apparatuses, and systems in which a processor includes an issue engine and an in-order execution pipeline. The issue engine categorizes operations as at least one of either a speculative operation which perform computations or an architectural operation which has potential to fault or cause an exception. Each architectural operation issues with an associated architectural micro-operation. A first micro-operation checks whether a first speculative operation is dependent upon an intervening first architectural operation. The in-order execution pipeline executes the speculative operation, the architectural operation, and the associated architectural micro-operations.
Claims12
A machine-readable medium that provides instructions, which when executed by a machine, cause the machine to perform operations comprising:
- issue a speculative load operation having a first address;
- issue a store operation having a second address, the speculative load operation being dependant on the store operation;
- and
- issue a check operation to determine whether the speculative load operation has been executed prior to executing the issued store operation if the first address overlaps with the second address.
A method of operating a processor, comprising:
- issue a speculative load operation having a first address;
- issue a store operation having a second address, the speculative load operation being dependant on the store operation;
- and
- issue a check operation to determine whether the speculative load operation has been executed prior to executing the issued store operation if the first address overlaps with the second address.
An apparatus, comprising:
- a processor to:
- issue a speculative load operation having a first address;
- issue a store operation having a second address, the speculative load operation being dependant on the store operation;
- and
- issue a check operation to determine whether the speculative load operation has been executed prior to executing the issued store operation if the first address overlaps with the second address.
A system, comprising:
- a processor to issue a speculative load operation having a first address, issue a store operation having a second address, the speculative load operation being dependant on the store operation, and issue a check operation to determine whether the speculative load operation has been executed prior to executing the issued store operation if the first address overlaps with the second address;
- a data bus coupled to the processor;
- and
- a non-volatile memory coupled to the data bus.
Dependencies are inferred from the claim text.