Programmable delayed dispatch in a multi-threaded pipeline
AssigneeMicrosoft Corporation
InventorSusan Carrie
Life of this patent
Estimating the term…
Abstract
Detecting a stall condition associated with processor instructions within one or more threads and generating a no-dispatch condition. The stall condition can be detected by hardware and/or software before and/or during processor instruction execution. The no-dispatch condition can be associated with a number of processing cycles and an instruction from a particular thread. As a result of generating the no-dispatch condition, processor instructions from other threads may be dispatched into the execution slot of an available execution pipeline. After a period of time, the instruction associated with the stall can be fetched and executed.
Claims20
A method for adding no-dispatch information to an instruction stream, comprising:
- accessing a set of instructions;
- detecting a stall condition in the set of instructions;
- and
- inserting no-dispatch information into the set of instructions, the no-dispatch information derived from the stall condition.
A system for processing instructions, comprising:
- one or more instruction fetch units able to provide a set of instructions;
- a dispatch unit configured to receive the set of instructions from said one or more instruction fetch units;
- and
- one or more execution pipelines configured to receive instructions from said dispatch unit,
- the dispatch unit able to delay dispatch of instructions to the one or more execution pipelines in response to receiving no-dispatch information in the set of instructions.
A system for processing instructions, comprising:
- one or more instruction fetch units able to provide a set of instructions;
- a dispatch unit configured to receive the set of instructions from said one or more instruction fetch units;
- a dispatch pre-decode able to receive the set of instructions from the one or more fetch units and generate no-dispatch information;
- and
- one or more execution pipelines configured to receive instructions from said dispatch unit,
- the dispatch unit able to delay dispatch of instructions to the one or more execution pipelines in response to receiving no-dispatch information from said dispatch pre-decode.
Dependencies are inferred from the claim text.