Device and method for correcting errors in a processor having two execution units

A processor comprising:

• a device for correcting errors in a processor, including:
• two execution units;
• registers, in which at least one of instructions and associated information is storable, the at least one of the instructions and the associated information being processed redundantly in both of the execution units, wherein the registers of the processor are divided into first registers and second registers, the first registers being arranged so that a specifiable state of the processor and contents of the second registers are derivable therefrom;
• a comparison arrangement to detect at least one of a deviation and an error by comparing the at least one of the instructions and the associated information;
• and
• a rollback arrangement which is arranged so that at least of an instruction and associated information in the first registers are rolled back and are at least one of executed anew and restored.

A method for correcting errors in a processor having two execution units, at least one of instructions and associated information being storable in registers, the method comprising:

• processing the instructions redundantly in both of the execution units;
• detecting at least one of a deviation and an error by comparing the at least one of the instructions and the associated information, wherein the registers of the processor are divided into first registers and second registers, a specifiable state of the processor and contents of the second registers being derivable from the first registers;
• and
• at least one of an instruction and associated information in the first registers being rolled back and at least one of executed anew and restored when an error occurs.