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US 2006/0190701 A1Published application
Data processor
AssigneeRenesas Technology Corp.
InventorsTakanobu Tsunoda, Bryan Atwood, Masashi Takada, Hiroshi Tanaka
Life of this patent
Estimating the term…
Abstract
There is provided at least one processor block including a plurality of load store interfaces (801, 804), a plurality of memory banks (821), an input/output port having at least one of an input port (850) and an output port (860), and a crossbar switch (810), and the crossbar switch connects the load store interface, the memory bank and the input/output port to each other and the load store interface constitutes a data processor in order to control a data transfer to the memory bank. Consequently, there is implemented a data processor having a high transfer throughput and a flexibility and efficiently treating stream data.
Claims30
A data processor comprising:
- at least one processor block,
- wherein the processor block includes a calculating portion having a plurality of calculating units and capable of switching their connecting forms and functions, a local memory portion having a plurality of banks capable of being accessed in parallel, an external interface portion, a bus switch portion and a control portion,
- a part of the calculating units in the calculating portion can generate a load request of an operation operand to the other calculating units and a store request of a result of a calculation carried out by the other calculating units, and
- the bus switch portion can select a connection among the calculating portion, the local memory portion and the external interface portion.
1 more element
A data processor comprising:
- a plurality of processor blocks,
- wherein the processor block includes a calculating portion having a plurality of calculating units and capable of switching their connecting forms and functions, and a local memory portion, and
- one of the processor blocks is connected to the other processor blocks.
A data processor comprising:
- a plurality of processor blocks,
- wherein the processor block includes a calculating portion having a plurality of calculating units and capable of switching their connecting forms and functions, and a local memory portion, and
- one of the processor blocks can be written to the local memory portions of the other processor blocks.
A data processor comprising:
- a calculating portion including a plurality of calculating cells for executing a calculation, their logical functions being defined based on configuration data;
- a plurality of data memories having a plurality of access ports capable of being operated in parallel and holding calculation data;
- a plurality of memory control circuits serving to control access of the corresponding data memory and having a control form defined based on configuration data;
- an external interface portion to be connected to the memory control circuit;
- a crossbar switch portion connecting the calculating portion to the memory control circuit and having a connecting form defined based on configuration data;
- and
- a control portion for carrying out a control for transferring the configuration data to the calculating cell, the memory control circuit and the crossbar switch portion and controlling their status transition,
- wherein the memory control circuit can accept a first access request given from the external interface portion to the data memory and a second access request given from the calculating cell to the data memory and an access response control procedure for responding to the first access request and the second access request can be varied based on the configuration data.
5 more elements
A data processor comprising:
- an internal bus;
- a flexible processor;
- a CPU;
- and
- an RAM,
- wherein the internal bus is connected to the flexible processor, the CPU and the RAM,
- wherein the flexible processor includes:
- a calculating portion having a plurality of calculating cells for executing a calculation, their logical function being defined based on configuration data;
- a plurality of data memories having a plurality of access ports capable of being operated in parallel and holding calculation data;
- a plurality of memory control circuits serving to control access of the corresponding data memory and having a control form defined based on configuration data;
- an external interface portion to be connected to the memory control circuit;
- a crossbar switch portion connecting the calculating portion to the memory control circuit and having a connecting form defined based on configuration data;
- and
- a control portion for carrying out such a control as to transfer the configuration data to the calculating cell, the memory control circuit and the crossbar switch portion and controlling their status transition,
- wherein the memory control circuit can accept a first access request given from the external interface portion to the data memory and a second access request given from the calculating cell to the data memory, and an access response control procedure for responding to the first access request and the second access request can be varied based on the configuration data,
- wherein the external interface portion is connected to the internal bus,
- wherein the CPU can execute a program stored in the RAM and can transfer data retained in the RAM from the external interface portion to the data memory, and
- wherein the CPU can transfer calculation result data obtained by the flexible processor retained in the data memory from the external interface portion to the RAM.
15 more elements
Dependencies are inferred from the claim text.