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AssigneeInternational Business Machines Corporation
InventorsRichard Arndt, George Daly, James Fields, Warren Maule
Estimating the term…
A method and apparatus for invalidating entries within a translation control entry (TCE) cache are disclosed. A host bridge is coupled between a group of processors and a group of adaptors. The host bridge includes a TCE cache. The TCE cache contains the most-recently use copies of TCEs in a TCE table located in a system memory. In response to a modification to a TCE in the TCE table by one of the processors, a memory mapped input/output (MMIO) Store is sent to a TCE invalidate register to specify an address of the modified TCE. The data within the TCE invalidate register is then utilized to generate a command for invalidating an entry in the TCE cache containing an unmodified copy of the modified TCE in the TCE table. The command is subsequently sent to the host bridge to invalidate the entry in the TCE cache.
A method for invalidating entries within a translation control entry (TCE) cache within a host bridge, wherein said host bridge is coupled between a plurality of processors and a plurality of adaptors, said method comprising:
An apparatus for invalidating entries within a translation control entry (TCE) cache within a host bridge, wherein said host bridge is coupled between a plurality of processors and a plurality of adaptors, said apparatus comprising:
An apparatus for invalidating entries within a translation control entry (TCE) cache within a host bridge, wherein said host bridge is coupled between a plurality of processors and a plurality of adaptors, said apparatus comprising:
Dependencies are inferred from the claim text.