Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag
OwnerDouglas Butler, Oscar Jones +1inventors
InventorsDouglas Butler, Oscar Jones, Michael Parris
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Abstract
A static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag provides a memory architecture comprising low cost DRAM memory cells that is available for system accesses 100% of the time and is capable of executing refreshes frequently enough to prevent data loss. Any subarray of the memory can be written from cache or refreshed at the same time any other subarray is read or written externally.
Claims61
An integrated circuit device comprising:
- a dynamic random access memory array comprising a plurality of memory subarrays;
- a cache operatively coupled to said plurality of memory subarrays for mirroring any one of said plurality of memory subarrays;
- and
- means for indicating which one of said plurality of memory subarrays is currently being mirrored by said cache.
An integrated circuit device comprising:
- a dynamic random access memory array comprising a plurality of memory subarrays;
- and
- a cache operatively coupled to said memory array for mirroring only one of said plurality of memory subarrays at a time.
An integrated circuit device comprising:
- a dynamic random access memory array comprising a plurality of memory subarrays;
- and
- a dynamic random access memory cache comprising a number of memory cells equal to that of each of said plurality of memory subarrays.
An integrated circuit device comprising:
- a dynamic random access memory array comprising a plurality of memory subarrays;
- a cache operatively coupled to said memory array for mirroring any one of said plurality of memory subarrays;
- an array internal address bus coupled to each of said plurality of memory subarrays;
- and
- a cache internal address bus coupled to said cache.
An integrated circuit device comprising:
- a dynamic random access memory array comprising a plurality of memory subarrays;
- a cache operatively coupled to said memory array for mirroring one of said plurality of memory subarrays;
- and
- an address control block for receiving addresses supplied externally to said integrated circuit device and coupled to said cache and said plurality of memory subarrays by an external address bus.
An integrated circuit device comprising:
- a dynamic random access memory array comprising a plurality of memory subarrays;
- and
- means for substantially concurrently accessing more than one of said memory subarrays.
An integrated circuit device comprising:
- a DRAM array comprising a plurality of subarrays;
- a cache having at least as many memory cells as that of each of said subarrays;
- means for refreshing any one of said subarrays substantially concurrently with an access to another one of said subarrays;
- means for writing data to said cache being read from said DRAM array;
- means for writing data to said cache instead of writing to said DRAM array;
- means for reading data from said cache instead of reading from said DRAM array;
- means for transferring data from said cache to any one of said subarrays substantially concurrently with an access to another one of said subarrays;
- means for indicating locations within said cache which contain valid data;
- means for indicating from which one of said plurality of subarrays said cache may be mirroring valid data;
- and
- control circuitry enabling the hiding of refresh operations to said DRAM array.
Dependencies are inferred from the claim text.