Sequential nibble burst ordering for data
AssigneeMicron Technology, Inc.
InventorJeffery Janzen
Life of this patent
Estimating the term…
Abstract
A combination of circuits for use in a memory device is comprised of a decode circuit responsive to a first portion of address information for identifying a word to be read or written. The decode circuit is further responsive to a second portion of the address information for identifying an order in which one or more portions of the identified word are to be read or written. An address sequencer routes at least one bit of the address information. A sequencer circuit is responsive to the address sequencer for ordering the plurality of data bits within each portion of the identified word.
Claims14
A combination of circuits for use in a memory device, comprising:
- a decode circuit responsive to a first portion of address information for identifying a word to be read or written, said decode circuit further responsive to a second portion of the address information for identifying an order in which one or more portions of said identified word are to be read or written, wherein each of said portions is comprised of a plurality of data bits and wherein for sequential burst mode operation each portion is comprised of a specific group of data bits;
- an address sequencer for routing at least one bit of the address information;
- and
- a sequencer circuit responsive to said address sequencer for ordering said plurality of data bits within each portion of said identified word.
A combination of circuits for use in a memory device, comprising:
- a decode circuit responsive to a first portion of address information for identifying a word to be read, said decode circuit further responsive to a second portion of the address information for identifying an order in which one or more portions of said word are read;
- an address sequencer for routing at least one bit of the address information;
- and
- a read sequencer responsive to said address sequencer for ordering said plurality of data bits within each portion of said identified word so as to enable a sequential burst output sequence independently of said internal prefetch architecture.
A combination of circuits for use in a memory device, comprising:
- a decode circuit responsive to column address bits CA3 through CAi for identifying a word to be written, said decode circuit further responsive to column address bit CA2 for identifying an order in which one or more portions of said identified word are to be written;
- an address sequencer for routing column address bit CA2;
- and
- a write sequencer circuit responsive to column address bit CA2 for ordering said plurality of data bits within each portion of said identified word.
Dependencies are inferred from the claim text.