US 2006/0190676 A1 · Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks

Abstract

A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time.

Claims111

Dependent claims

An integrated circuit device comprising:

a dynamic random access memory array comprising a plurality of memory subarrays;
a cache for mirroring one of said plurality of memory subarrays;
a data read register for maintaining data that has been read from said memory array;
and
a data write register for maintaining data that has been read from said cache.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/064,354Filed 23 Feb 2005

Published

24 Aug 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 12/0804
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: with main…
G11C 11/406
Forming cells needing refreshing or charge regeneration, i.e. dynamic cells: management or control of the refreshing or charge-regeneration cycles
G11C 11/40607
Management or control of the refreshing or charge-regeneration cycles: refresh operations in memory devices with an internal cache or data buffer
G11C 11/4076
For memory cells of the field-effect type: timing circuits

Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks

Life of this patent

Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks

Life of this patent

Abstract

Claims111