Hub chip for connecting one or more memory chips
OwnerPeter Poechmuellerinventor
Life of this patent
Estimating the term…
Abstract
The invention relates to a hub chip for connecting one or more memory chips via a respective memory chip interface, having an address input for connecting the hub chip to an address bus and having an address output for connection to a further address bus, having an address decoder unit configured to use an address applied to the address input to address one of the connected memory chips or to apply the applied address to the address output, characterized by an error recognition unit configured to use provided checking data to detect an error in a memory area of the one or more memory chips.
Claims21
A hub chip for connecting one or more memory chips via a memory chip interface, comprising;
- an address input for connecting the hub chip to an address bus;
- an address output for connection to a further address bus;
- an address decoder unit configured to utilize an address applied to the address input to selectively address one of the connected memory chips and apply the applied address to the address output;
- and
- an error recognition unit configured to utilize provided checking data to detect an error in a memory area of the one or more memory chips.
A memory module, comprising:
- one or more memory chips;
- and
- a hub chip connected to the one or more memory chips via a memory chip interface, the hub chip comprising:
- an address input for connecting the hub chip to an address bus;
- an address output for connection to a further address bus;
- an address decoder unit configured to utilize an address applied to the address input to selectively address one of the connected memory chips and apply the applied address to the address output;
- and
- an error recognition unit configured to utilize provided checking data to detect an error in a memory area of the one or more memory chips.
A memory system, comprising:
- one or more memory modules;
- a memory controller;
- and
- an address bus connecting the memory controller to a first one of the one or more memory modules;
- each memory module comprising:
- one or more memory chips;
- and
- a hub chip connected to the one or more memory chips via a memory chip interface, the hub chip comprising:
- an address input for connecting the hub chip to an address bus;
- an address output for connection to a further address bus for connecting to subsequent memory modules;
- an address decoder unit configured to utilize an address applied to the address input to selectively address one of the connected memory chips and apply the applied address to the address output;
- and
- an error recognition unit configured to utilize provided checking data to detect an error in a memory area of the one or more memory chips.
Dependencies are inferred from the claim text.