US 2006/0190667 A1 · Pipeline bit handling circuit and method for a bus bridge

Abstract

A circuit and method to provide pipeline bit handling across a bus bridge between two different buses. In a preferred embodiment, the pipeline bit handling circuit provides rule enforcement for a P-bit address modifier across a bus bridge between two different buses with different rules for the P-bit address modifier. In a bus domain where pipeline transactions are allowed if the P-Bit is asserted and are not allowed if the P-Bit is not asserted, embodiments herein allow a master bus device to ensure that all bus devices will see a P=0 command with a defined minimum spacing to any other P=0 command. The required separation for P=0 commands is maintained within the bus bridge. In the preferred embodiments, the separation between P=0 commands is maintained by immediately retrying P=0 commands rather than spacing snoop requests.

Claims18

Dependent claims

A pipeline bit handling circuit in a computer bus bridge between a first bus and a second bus comprising:

a pipeline bit command detector that detects a command containing an asserted pipeline bit on the first bus;
a pipeline bit retry circuit that determines when to assert command retry on the first bus;
and
a pipeline command complete detect circuit to signal the pipeline bit retry circuit that a pipeline command on the first bus is complete to cause the pipeline bi retry circuit to assert command retry on the first bus.

1 more element

Dependencies are inferred from the claim text.

Pipeline bit handling circuit and method for a bus bridge

Life of this patent

Pipeline bit handling circuit and method for a bus bridge

Life of this patent

Abstract

Claims18