Transaction flow control mechanism for a bus bridge
AssigneeInternational Business Machines Corporation
InventorsClarence Ogilvie, Charles Woodruff
Life of this patent
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Abstract
A transaction flow control mechanism is disclosed for a bus bridge in a high speed computer system with a high speed interface for a graphics processor. A preferred embodiment provides a flow control mechanism for the bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and a high speed interface. A preferred embodiment of the invention is a bus transceiver on a multi-chip module.
Claims24
A flow control mechanism for a bus bridge that provides conversion between a first bus and a second bus in a computer processor system comprising:
- a command and tag FIFO that stores a portion of a command sent from the first bus to the second bus until a reflected command is received from the second bus.
A flow control mechanism for a bus bridge that provides conversion between an API bus and a MPI bus in a computer processor system comprising:
- a command and tag FIFO that stores a portion of a command sent from the API bus to the MPI bus until a reflected command is received from the MPI bus.
A computer processor system comprising:
- a processor with an first bus;
- a transceiver with a bridge that provides a conversion between the first bus and a second bus;
- and
- wherein the bridge includes a flow control mechanism comprising a command and tag FIFO that stores a portion of a command sent from the first bus to the second bus until a reflected command is received from the second bus.
A method of transaction flow control for a bus bridge in a computer processor system comprising the steps of:
- storing a portion of a command and tag sent from a first bus in a FIFO until a reflected command is received from the second bus;
- and
- comparing a reflected command from the second bus to determine if it is the same as a command stored in the FIFO.
A method of transaction flow control for a bus bridge in a computer processor system comprising the steps of:
- storing a portion of a command and tag sent from a API bus in a FIFO until a reflected command is received from a MPI bus;
- and
- comparing a reflected command from the MPI bus to determine if it is the same as a command stored in the FIFO.
Dependencies are inferred from the claim text.