Computer system bus bridge
AssigneeInternational Business Machines Corporation
InventorsGiora Biran, Robert Drehmel, Robert Horton, Mark Kautzman, Jamie Kuesel, Ming-i Lin, Eric Mejdrich, Clarence Ogilvie, Charles Woodruff
Life of this patent
Estimating the term…
Abstract
A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.
Claims33
A bus bridge in a computer processor system that provides conversion between a first bus and an second bus comprising:
- a first bus to second bus command and data conversion unit that converts commands and data from the first bus to the second bus;
- a second bus to first bus command and data conversion unit that converts commands and data from the second bus to the first bus;
- and
- a snoop response unit that supports snoop requests to maintain data coherency.
A bus bridge in a computer processor system that provides conversion between an API bus and an MPI bus comprising:
- an API to MPI command and data conversion unit comprising:
- a read buffer assign counter and a write buffer assign counter;
- command and tag conversion logic to convert commands and tags from the API bus to the MPI bus;
- a read command counter, a write command counter and a credit counter;
- logic for the read command counter, the write command counter and the credit counters to signal to the API bus that a read command, a write command or a credit is available;
- an array of read intervention buffers and an array of write buffers that hold data until it is sent out on the MPI bus, wherein the read intervention buffers and the write buffers comprise an array of registers for each buffer with a load address generator circuit to hold an address to access the array of registers;
- an MPI to API command and data conversion unit comprising:
- an array of read buffers;
- command and tag conversion logic to convert commands and tags from the MPI bus to the API bus;
- and
- a snoop response unit with snoop response conversion logic and a read command counter.
A computer processor system comprising:
- at least one processor with an API bus;
- a transceiver with a bridge;
- and
- an output bus,
- wherein the bridge provides a conversion between the API bus and the output bus.
The computer processor system 10 wherein the API to MPI command and data conversion unit further comprises a read command counter, a write command counter and a credit counter and logic for the read command counter, the write command counter and the credit counters to signal to the API bus that a read command, a write command or a credit is available.
A method for bridging between an API bus and an MPI bus in a computer processor system, the method comprising the steps of:
- translating API to MPI read commands initiated on the API bus to the MPI bus;
- translating API to MPI write commands initiated on the API bus to the MPI bus;
- translating MPI to API read commands with modified intervention initiated on the MPI bus to the API bus;
- and
- translating MPI to API commands only transactions from the MPI bus to the API bus.
Dependencies are inferred from the claim text.