Method and apparatus for testing, characterizing and monitoring a chip interface using a second data path

A circuit card assembly for a digital data system, comprising:

• a circuit card;
• an integrated circuit module mounted to the circuit card;
• at least one intermodule communication line connecting the module to at least one other integrated circuit module;
• a data receiver circuit in the module for receiving data transmitted across the at least one intermodule communication line from another integrated circuit module and
• transmitting the data across a primary data path and a secondary data path;
• a first latch in the module for latching the data transmitted across the primary data path based on a first clock signal;
• a second latch in the module for latching the data transmitted across the secondary data path based on a second clock signal, the second clock signal being skewed relative to the first clock signal;
• comparison logic in the module that compares the data latched from the primary data path with the data latched from the secondary data path;
• logging logic in the module that records the occurrence of any miscompares in the comparison logic.

An integrated circuit module for a digital data system, comprising:

• an intermodule interface for communicating with at least one other integrated circuit module of the digital data system, the intermodule interface comprising at least one intermodule communication line connection;
• a data receiver circuit for receiving data transmitted across the at least one intermodule communication line from another integrated circuit module and transmitting the data across a primary data path and a secondary data path;
• a first latch for latching the data transmitted across the primary data path based on a first clock signal;
• a second latch for latching the data transmitted across the secondary data path based on a second clock signal, the second clock signal being skewed relative to the first clock signal;
• comparison logic that compares the data latched from the primary data path with the data latched from the secondary data path;
• logging logic that records the occurrence of any miscompares in the comparison logic.

A method for characterizing an inter-chip interface, comprising:

• (a) transmitting data from a first integrated circuit module to a second integrated circuit module across at least one intermodule communication line;
• (b) receiving the data transmitted across the at least one intermodule communication line and transmitting the data across a primary data path and a secondary data path;
• (c) latching the data transmitted across the primary data path based on a first clock signal;
• (d) latching the data transmitted across the secondary data path based on a second clock signal, the second clock signal being skewed relative to the first clock signal;
• (e) comparing the data latched from the primary data path with the data latched from the secondary data path;
• (f) logging any miscompares between the data latched from the primary data path and the data latched from the secondary data path.

A computer program product, comprising:

• (a) fabrication instructions that direct the creation of an integrated circuit module for a digital data system, comprising:
• an intermodule interface for communicating with at least one other integrated circuit module of the digital data system, the intermodule interface comprising at least one intermodule communication line connection;
• a data receiver circuit for receiving data transmitted across the at least one intermodule communication line from another integrated circuit module and transmitting the data across a primary data path and a secondary data path;
• a first latch for latching the data transmitted across the primary data path based on a first clock signal;
• a second latch for latching the data transmitted across the secondary data path based on a second clock signal, the second clock signal being skewed relative to the first clock signal;
• comparison logic that compares the data latched from the primary data path with the data latched from the secondary data path;
• logging logic that records the occurrence of any miscompares in the comparison logic;
• and
• (b) a signal bearing media bearing the fabrication instructions.