Asynchronous jitter reduction technique
AssigneeGrass Valley (U.S.) Inc.
InventorRobert Castlebary
Life of this patent
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Abstract
The amount of jitter incurred when reading data written into a FIFO can be reduced by clocking the FIFO with Read Clock pulses at a frequency χ ƒn where χ is a whole integer and ƒn is the frequency at which the memory is clocked to write data. Read Addresses are applied to the FIFO at a frequency on the order of ƒn to identify successive locations in the memory for reading when the memory is clocked with read clocked pulses to enable reading of samples stored at such successive locations. The duration of at least one successive Read Addresses is altered in response to memory usage status to maintain memory capacity below a prescribed threshold.
Claims12
A method for reading data from a memory to achieve reduced jitter, comprising the steps of:
- applying successive read clock pulses to the memory at a frequency of xƒn where χ is a whole integer and ƒn is the frequency at which the memory is clocked to write data;
- applying successive Read Addresses to the memory at a frequency on the order of ƒn to identify successive locations in the memory for reading when the memory is clocked with read clocked pulses to enable reading of samples stored at such successive locations;
- and
- altering the duration of at least one successive Read Addresses in response to memory usage status to maintain memory capacity within at least one a prescribed threshold.
A system for reading stored data to achieve reduced jitter, comprising:
- a memory into which data is written and from which data is read;
- a clock applying successive read clock pulses to the memory at a frequency of xƒn where x is a whole integer and ƒn is the frequency at which the memory is clocked to write data;
- a memory address generator for applying successive Read Addresses to the memory at a frequency on the order of ƒn to identify successive locations in the memory for reading when the memory is clocked with read clocked pulses to enable reading of samples stored at such successive locations;
- and for altering the duration of at least one successive Read Addresses in response to memory usage status to maintain memory capacity within at least one a prescribed threshold.
Dependencies are inferred from the claim text.