Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations
AssigneeInternational Business Machines Corporation
InventorsGeorge Daly, James Fields
Life of this patent
Estimating the term…
Abstract
A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.
Claims15
A method for invalidating cache lines during a direct memory access (DMA) Write operation by a peripheral device in a multiprocessor system, wherein said multiprocessor system includes a plurality of processors, each having a cache memory, said method comprising:
- issuing a multi-cache line DMA request by a peripheral device;
- snooping said multi-cache line DMA request by said cache memories;
- determining whether or not any of said cache memories include a copy of data stored in a plurality of system memory locations to which said multi-cache line DMA request are directed;
- in response to one of said cache memories includes a copy of data stored in a plurality of system memory locations to which said multi-cache line DMA request are directed, consecutively invalidating a plurality of cache lines within said one of said cache memories.
An apparatus for invalidating cache lines during a direct memory access (DMA) Write operation by a peripheral device in a multiprocessor system, wherein said multiprocessor system includes a plurality of processors, each having a cache memory, said apparatus comprising:
- means for issuing a multi-cache line DMA request by a peripheral device;
- means for snooping said multi-cache line DMA request by said cache memories;
- means for determining whether or not any of said cache memories include a copy of data stored in a plurality of system memory locations to which said multi-cache line DMA request are directed;
- in response to one of said cache memories includes a copy of data stored in a plurality of system memory locations to which said multi-cache line DMA request are directed, means for consecutively invalidating a plurality of cache lines within said one of said cache memories.
A computer program product for invalidating cache lines during a direct memory access (DMA) Write operation by a peripheral device in a multiprocessor system, wherein said multiprocessor system includes a plurality of processors, each having a cache memory, said computer program product comprising:
- program code means for issuing a multi-cache line DMA request by a peripheral device;
- program code means for snooping said multi-cache line DMA request by said cache memories;
- program code means for determining whether or not any of said cache memories include a copy of data stored in a plurality of system memory locations to which said multi-cache line DMA request are directed;
- in response to one of said cache memories includes a copy of data stored in a plurality of system memory locations to which said multi-cache line DMA request are directed, program code means for consecutively invalidating a plurality of cache lines within said one of said cache memories.
Dependencies are inferred from the claim text.