Binary polynomial multiplier

In a processor core, a method for performing polynomial arithmetic, the method comprising:

• fetching an instruction to perform an operation from a data store;
• reading one or more registers;
• performing the operation using a multiply unit, the multiply unit comprising:
• at least one input data path for receiving one or more input operands to the multiply unit;
• an arithmetic multiplier connected to receive the one or more input operands;
• a binary polynomial multiplier connected to receive the one or more input operands and including components separate and distinct from components of the arithmetic multiplier;
• permutation logic connected to receive the one or more input operands and operable to produce an output comprising a permutation of the one or more input operands;
• and
• a multiply unit output data path connected to receive an output of the arithmetic multiplier, connected to receive an output of the binary polynomial multiplier, and connected to receive the output of the permutation logic,
• wherein the multiply unit output data path includes one or more components to separately select the output of the arithmetic multiplier, the output of the binary polynomial multiplier or the output of the permutation logic to form a result.

A computer-readable medium comprising a microprocessor core embodied in software, the microprocessor core including a multiply-divide unit, the multiply-divide unit comprising:

• at least one input data path for receiving one or more input operands to the multiply unit;
• an arithmetic multiplier connected to receive the one or more input operands;
• a binary polynomial multiplier connected to receive the one or more input operands and including components separate and distinct from components of the arithmetic multiplier;
• permutation logic connected to receive the one or more input operands and operable to produce an output comprising a permutation of the one or more operands;
• and
• a multiply unit output data path connected to receive an output of the arithmetic multiplier, connected to receive an output of the binary polynomial multiplier, and connected to receive the output of the permutation logic,
• wherein the multiply unit output data path includes one or more components to separately select the output of the arithmetic multiplier, the output of the binary polynomial multiplier or the output of the permutation logic to form a result.