Digital signal processing element having an arithmetic logic unit

A DSP circuit comprising:

• a first register block and a second register block, each register block coupled to a first multiplexer of a first plurality of multiplexers, the first plurality of multiplexers controlled by a first opmode signal;
• a third register coupled to a second multiplexer of the first plurality of multiplexers;
• and
• a first arithmetic logic unit (ALU) coupled to the first plurality of multiplexers and controlled by a second opmode signal.

A digital signal processing block comprising:

• a first digital signal processing element comprising:
• a first multiplier circuit;
• a first plurality of input selection circuits coupled to the first multiplier circuit, the first plurality of multiplexers controlled by a first opmode;
• and
• a first arithmetic logic unit coupled to the first plurality of input selection circuits, the first arithmetic logic unit configured by a second opmode;
• and
• a second digital signal processing element comprising:
• a second multiplier circuit;
• a second plurality of input selection circuits coupled to the second multiplier circuit, the second plurality of input selection circuits controlled by a third opmode;
• and
• a second arithmetic logic unit coupled to the second plurality of input selection circuits and to an input selection circuit of the first plurality of input selection circuits, the second arithmetic logic unit programmed by a fourth opmode.