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AssigneeQuickturn Design Systems, Inc.
InventorsWilliam Beausoleil, Mitchell Poplack, Steven Comfort, Beshara Elmufdi
Estimating the term…
The present system and methods are directed to the interconnection of clusters of emulation processors comprising emulation processors in a software-driven hardware design verification system. The processors each output one NBO output signal. The clusters are interconnected by partitioning a common NBO bus into a number of smaller NBO busses, each carrying unique NBO signals but together carrying every NBO. Each of the smaller NBO busses are passed into a series of multiplexers, each dedicated to a particular processor. The multiplexers select a signal for output back to the emulation clusters. The multiplexers that handle these smaller NBO busses are narrower than was previously required, thus reducing the amount of power, interconnect, and area required by the multiplexer array and dedicated interconnect.
A system for interconnecting processors in a processor-based hardware design verification system, comprising:
A method for interconnecting emulation processors in a hardware design verification system, comprising the steps of:
Dependencies are inferred from the claim text.