Verilog HDL simulation model for retain time

A computer program product for making a simulator simulating retain and access time of an output port of a circuit, the computer program product comprising:

• program code for detecting transition of a input/bidirectional pin;
• program code for setting a variable to on in a non-blocking way in the retain time of the circuit, so that an access time model is enabled, and assigning a register to be a value of the output port in non-blocking way, wherein the value is assigned upon the transition of the input/bidirectional pin;
• program code for waiting until the end of retain time;
• program code for setting a variable to off in a blocking way, disabling the access time model;
• program code for assigning the output port to be unknown in a blocking way;
• program code for assigning the output port the value stored in the register in a non-blocking way;
• and
• program code for setting a variable on in a non-blocking way, enabling the access time model.