Integrated circuit layout critical area determination using voronoi diagrams and shape biasing
AssigneeInternational Business Machines Corporation
InventorsRobert Allen, Peter Chan, Evanthia Papadopoulou, Sarah Prue, Mervyn Tan
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Abstract
Method, system and program product for determining a critical area in a region of an integrated circuit layout using Voronoi diagrams and shape biasing. The method includes the steps of generating a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias; and determining the critical area for the region using the biased Voronoi diagram.
Claims20
A method of determining critical area in a region of an integrated circuit design, the method comprising the steps of:
- generating a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias;
- and
- determining the critical area for the region using the biased Voronoi diagram.
A system for determining critical area in a region of an integrated circuit design, the system comprising:
- means for generating a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias;
- and
- means for determining the critical area for the region using the biased Voronoi diagram.
A computer program product comprising a computer useable medium having computer readable program code embodied therein for determining critical area in a region of an integrated circuit design, the program product comprising:
- program code configured to generate a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias;
- and
- program code configured to determine the critical area for the region using the biased Voronoi diagram.
Dependencies are inferred from the claim text.