Body capacitor for SOI memory description

A method of fabricating a semiconductor structure comprising

• providing a structure that includes a patterned material stack located atop a patterned Si-containing layer, said patterned Si-containing layer is located on a buried insulating layer of a silicon-on-insulator substrate;
• forming a dielectric on exposed sidewalls of at least said patterned Si-containing layer;
• forming isolation regions on exposed areas of said buried insulating layer that lie adjacent to said patterned Si-containing layer;
• providing a recess in a portion of said isolation regions through said buried insulating layer and forming a sidewall capacitor plate in said recess;
• forming a plurality of transistors on said patterned Si-containing layer, each transistor comprising a wordline gate conductor and underlying source/drain diffusions;
• and
• forming a source line atop one of said diffusions and forming a bitline stud and a bitline atop said other diffusion, wherein said bitline stud separates a pair of adjacent wordline gate conductors, and said source/drain diffusions, said wordline gate conductor and said capacitor plate have edges that are aligned to each other.

A memory cell layout comprising

• a plurality of transistors, each including a wordline gate conductor, located on a surface of a patterned Si-containing layer of a silicon-on-insulator substrate, wherein a bitline stud that extends to an overlaying bitline is in contact with one of said source/drain diffusions;
• a source line located atop said patterned Si-containing layer adjacent to selected transistors, said source line is in contact with another of said source/drain diffusions;
• and
• a capacitor plate beneath each wordline gate conductor and located within said patterned Si-containing layer and extending down through an underlying buried insulating layer, wherein said source/drain diffusions, said wordline gate conductor and said capacitor plate have edges that are aligned to each other, and each wordline gate conductor gates a cell in alternate crossing bitlines.