Methods of fabricating contact regions for FET incorporating SiGe
AssigneeAmberWave Systems Corporation
InventorEugene Fitzgerald
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Abstract
Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
Claims21
1-36. (canceled)
A method of fabricating contact regions for a FET, the method comprising:
- providing a substrate comprising at least one of Si, SiGe, and Ge;
- providing a gate stack disposed above the substrate, the gate stack defining a channel region disposed thereunder,
- epitaxially depositing a SiGe layer in at least one area of the substrate adjacent to the gate stack, the SiGe layer being at least partially relaxed by the introduction of crystalline defects therein;
- providing a metal layer over the SiGe layer;
- and
- reacting the metal layer with the SiGe layer to form a region comprising at least one of silicide and silicide/germanicide.
A method of fabricating contact regions for a FET, the method comprising:
- providing a substrate comprising at least one of Si, SiGe, and Ge;
- providing a gate stack disposed above the substrate, the gate stack defining a channel region disposed thereunder, the channel region comprising a strained semiconductor material;
- epitaxially depositing a strained SiGe layer in at least one area of the substrate adjacent to the gate stack;
- providing a metal layer over the strained SiGe layer;
- and
- reacting the metal layer with the SiGe layer to form a region comprising at least one of silicide and silicide/germanicide.
Dependencies are inferred from the claim text.