Semiconductor device having a merged region and method of fabrication

A method for forming a semiconductor device, the method comprising:

• forming an insulated gate electrode pattern on a well region;
• forming a first-concentration impurity region adjacent first and second sides of the gate pattern, the first side being opposite to the second side;
• forming a sidewall spacer on sidewalls of the gate pattern;
• ion implanting impurities into the resulting structure to form a second-concentration impurity region under the second side of the gate pattern adjacent the sidewall spacer;
• and
• forming a silicide layer within the well region adjacent the sidewall spacer,
• wherein at least a part of the silicide layer adjacent the first side of the gate pattern contacts a portion of the well region to bias the well region;

A semiconductor device comprising:

• a first transistor and a second transistor having an isolation region disposed therebetween, the first and second transistors respectively formed on first and second well regions, the first transistor including:
• a first insulated gate electrode pattern formed on the first well region of a first-conductivity type,
• a first sidewall spacer formed on sidewalls of the first gate pattern,
• a first source region and a first drain region of a second-conductivity type formed adjacent opposite sides of the first gate pattern, the first source region including:
• a first-concentration impurity region of a second conductivity type formed under the first sidewall spacer, and a first silicide layer formed within the first well region,
• wherein at least a part of the first silicide layer contacts a portion of the first well region for biasing the first well region;
• and
• the second transistor including:
• a second insulated gate electrode pattern formed on the second well region of a second-conductivity type,
• a second sidewall spacer formed on sidewalls of the second gate pattern;
• a second source region and a drain region of a first-conductivity type formed adjacent opposite sides of the second gate pattern, the second source region including:
• a second first-concentration impurity region of a first conductivity type formed under the second sidewall spacer, and
• a second silicide layer formed within the second well region,
• wherein at least a part of the second silicide layer contacts a portion of the second well region for biasing the second well region.