Method of forming dual polysilicon gate of semiconductor device

Abstract

In a method of forming a dual polysilicon gate of a semiconductor device, a polysilicon layer is formed on a substrate divided into an NMOS region and a PMOS region. Then, a p-type impurity is implanted in the PMOS region. A thermal annealing process is performed that causes generation of a compound material at a top surface of the polysilicon layer in the PMOS region as a result of bonding between the p-type impurity and the polysilicon layer. A cleaning process is then performed. During the cleaning process, the compound material decreases an etch rate in the PMOS region, so that a height of the polysilicon layer in the NMOS region is reduced relative to that of the polysilicon layer in the PMOS region. Accordingly, an intended range of a threshold voltage can be obtained by blocking the p-type impurity in the PMOS region from penetrating into a gate insulation layer. Also, by maintaining an increased height of a gate transmission material in the cell region, a resistance increase is thereby prevented.

Dependencies are inferred from the claim text.