# US 2006/0189075 A1 · Method of manufacturing semiconductor integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2006/0189075 A1 - Document ID: US20060189075A1 - Status: Published application - Kind: A1 - Application number: 11/356,930 - Filed: 2006-02-17 - Published: 2006-08-24 - Earliest claimed: 2005-02-22 - Assignees: Sony Corporation - Inventors: Michihiro Kanno - Web page: https://patentgrep.com/patent/US20060189075A1 ## CPC - H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions} - H10B 10/00: Static random access memory [SRAM] devices - H10B 10/12: {comprising a MOSFET load element} - H10D 30/792: {comprising applied insulating layers, e.g. stress liners} - H10D 84/0167: {Manufacturing their channels} - H10D 84/0172: {Manufacturing their gate conductors} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having N-type and P-type FETS, and the memory array part having N-type and P-type FETS, includes the steps of forming N-type and P-type FETs constituting the logic part and the memory array part, thereafter sequentially forming a first insulation film having a tensile stress and a second insulation film on the whole surface, selectively removing the second insulation film and the first insulation film present on the upper side of the region of the P-type FET constituting the logic part, then forming a third insulation film having a compressive stress on the whole surface, and thereafter selectively removing the third insulation film present on the upper side of the region of the N-type FET constituting the logic part and the third insulation film present on the upper side of the regions of the N-type and P-type FETs constituting the memory array part. ## Claims ### Claim 1 A method of manufacturing a semiconductor integrated circuit comprising a logic part and a memory array part, said logic part comprised of an N channel type field effect transistor and a P channel type field effect transistor, and said memory array part comprised of an N channel type field effect transistor and a P channel type field effect transistor, said method comprising the steps of: (A) forming gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said logic part, and gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said memory array part, in a semiconductor substrate; (B) forming a first insulation film having a tensile stress on the whole surface and forming a second insulation film on said first insulation film; (C) selectively removing said second insulation film and said first insulation film present on the upper side of the region of said P channel type field effect transistor constituting said logic part; (D) forming a third insulation film having a compressive stress on the whole surface; and (E) selectively removing said third insulation film present on the upper side of the region of said N channel type field effect transistor constituting said logic part and said third insulation film present on the upper side of the regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said memory array part. ### Claim 2 (depends on 1) The method of manufacturing a semiconductor integrated circuit as set forth in claim 1, wherein subsequently to said step (E), ion implantation for relaxation of tensile stress is applied to said first insulation film on the region of said P channel type field effect transistor constituting said memory array part. ### Claim 3 (depends on 1) The method of manufacturing a semiconductor integrated circuit as set forth in claim 1, wherein said first insulation film and said third insulation film are each comprised of a silicon nitride film, and said second insulation film is comprised of a silicon oxide film. ### Claim 4 A method of manufacturing a semiconductor integrated circuit comprising a logic part and a memory array part, said logic part comprised of an N channel type field effect transistor and a P channel type field effect transistor, and said memory array part comprised of an N channel type field effect transistor and a P channel type field effect transistor, said method comprising the steps of: (A) forming gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said logic part, and gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said memory array part, in a semiconductor substrate; (B) forming a first insulation film having a tensile stress on the whole surface and forming a second insulation film on said first insulation film; (C) selectively removing said second insulation film and said first insulation film present on the upper side of the region of said P channel type field effect transistor constituting said logic part; (D) forming a third insulation film having a compressive stress on the whole surface; and (E) applying ion implantation for relaxation of compressive stress to said third insulation film present on the upper side of the region of said N channel field effect transistor constituting said memory array part, and selectively removing said third insulation film present on the upper side of the region of said N channel type field effect transistor constituting said logic part. ### Claim 5 (depends on 4) The method of manufacturing a semiconductor integrated circuit as set forth in claim 4, wherein in any step between said step (B) and said step (D), ion implantation for relaxation of tensile stress is applied to said first insulation film present on the region of said P channel type field effect transistor constituting said memory array part. ### Claim 6 (depends on 4) The method of manufacturing a semiconductor integrated circuit as set forth in claim 4, wherein said first insulation film and said third insulation film are each comprised of a silicon nitride film, and said second insulation film is comprised of a silicon oxide film. ### Claim 7 A method of manufacturing a semiconductor integrated circuit comprising a logic part and a memory array part, said logic part comprised of an N channel type field effect transistor and a P channel type field effect transistor, and said memory array part comprised of an N channel type field effect transistor and a P channel type field effect transistor, said method comprising the steps of: (A) forming gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said logic part, and gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said memory array part, in a semiconductor substrate; (B) forming a first insulation film having a tensile stress on the whole surface and forming a second insulation film on said first insulation film; (C) selectively removing said second insulation film present on the upper side of said regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said logic part; (D) selectively removing said first insulation film present on said region of said P channel type field effect transistor constituting said logic part; (E) forming a third insulation film having a compressive stress on the whole surface; and (F) selectively removing said third insulation film present on the upper side of said region of said N channel type field effect transistor constituting said logic part and said third insulation film present on the upper side of said regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said memory array part. ### Claim 8 (depends on 7) The method of manufacturing a semiconductor integrated circuit as set forth in claim 7, wherein subsequently to said step (F), ion implantation for relaxation of tensile stress is applied to said first insulation film on the region of said P channel type field effect transistor constituting said memory array part. ### Claim 9 (depends on 7) The method of manufacturing a semiconductor integrated circuit as set forth in claim 7, wherein said first insulation film and said third insulation film are each comprised of a silicon nitride film, and said second insulation film is comprised of a silicon oxide film. ### Claim 10 A method of manufacturing a semiconductor integrated circuit comprising a logic part and a memory array part, said logic part comprised of an N channel type field effect transistor and a P channel type field effect transistor, and said memory array part comprised of an N channel type field effect transistor and a P channel type field effect transistor, said method comprising the steps of: (A) forming gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said logic part, and gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said memory array part, in a semiconductor substrate; (B) forming a first insulation film having a tensile stress on the whole surface and forming a second insulation film on said first insulation film; (C) selectively removing said second insulation film present on the upper side of the regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said logic part; (D) selectively removing said first insulation film present on the region of said P channel type field effect transistor constituting said logic part; (E) forming a third insulation film having a compressive stress on the whole surface; and (F) applying ion implantation for relaxation of compressive stress to said third insulation film present on the upper side of the region of said N channel type field effect transistor constituting said memory array part, and selectively removing said third insulation film present on the upper side of the region of said N channel type field effect transistor constituting said logic part. ### Claim 11 (depends on 10) The method of manufacturing a semiconductor integrated circuit as set forth in claim 10, wherein in any step between said step (B) and said step (D), ion implantation for relaxation of tensile stress is applied to said first insulation film present on the region of said P channel type field effect transistor constituting said memory array part. ### Claim 12 (depends on 10) The method of manufacturing a semiconductor integrated circuit as set forth in claim 10, wherein said first insulation film and said third insulation film are each comprised of a silicon nitride film, and said second insulation film is comprised of a silicon oxide film. ### Claim 13 A method of manufacturing a semiconductor integrated circuit comprising a logic part and a memory array part, said logic part comprised of an N channel type field effect transistor and a P channel type field effect transistor, and said memory array part comprised of an N channel type field effect transistor and a P channel type field effect transistor, said method comprising the following steps: (A) forming gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said logic part, and gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said memory array part, in a semiconductor substrate; (B) forming a first insulation film having a tensile stress on the whole surface and forming a second insulation film on said first insulation film; (C) selectively removing said second insulation film and said first insulation film present on the upper side of the region of said N channel type field effect transistor constituting said logic part; (D) forming a third insulation film having a compressive stress on the whole surface; and (E) selectively removing said third insulation film present on the upper side of the region of said P channel type field effect transistor constituting said logic part, wherein between any two of said steps (B) to (D), ion implantation for relaxation of compressive stress is applied to said first insulation film present on the region of said N channel type field effect transistor constituting said memory array part. ### Claim 14 (depends on 13) The method of manufacturing a semiconductor integrated circuit as set forth in claim 13, wherein after said third insulation film having the tensile stress is formed, ion implantation for relaxation of tensile stress is applied to said third insulation film present on the upper side of the region of said P channel type field effect transistor constituting said memory array part. ### Claim 15 (depends on 13) The method of manufacturing a semiconductor integrated circuit as set forth in claim 13, wherein said first insulation film and said third insulation film are each comprised of a silicon nitride film, and said second insulation film is comprised of a silicon oxide film.